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Diseño de un amplificador riel a riel con tecnología CMOS 0,18 μm

This paper shows the full analysis, design and simulation of a 3.3 V CMOS input/output rail to rail or R-R operational amplifier using the design kit for the Synopsys tools. The technology used was CMOS TSMC 0.18μm whose cost is low for academic purposes. This paper details the complementary input s...

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Bibliographic Details
Institution:Universidad EIA
Main Authors: Hernández, Diego F., Antolínez, Juan F., Pineda, Elkin Y., Yamhure, German, Paéz, Carlos I.
Format: Objeto de aprendizaje
Language:Español
Published: Fondo Editorial EIA 2013-11-13
Subjects:
REI00184
CIRCUITOS INTEGRADOS LINEALES
LINEAR INTEGRATED CIRCUITS
ENERGÍA
ENERGY
VLSI
AMPLIFICADOR CARRIL A CARRIL
CMOS
LAYOUT
RAIL TO RAIL OPERATIONAL AMPLIFIER
Online Access:https://repository.eia.edu.co/handle/11190/135
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Summary:This paper shows the full analysis, design and simulation of a 3.3 V CMOS input/output rail to rail or R-R operational amplifier using the design kit for the Synopsys tools. The technology used was CMOS TSMC 0.18μm whose cost is low for academic purposes. This paper details the complementary input stage R-R, the summing circuit and the R-R output stage class AB. At last the final layout and the results of simulation are shown.
Physical Description:15 p.
ISSN:ISSN 17941237